IDE/CF Driver
Pin Name(s)
A00, A01, A02, -CS0, -CS1
-IORD
-IOWR
-IORDY
INTRQ
-RESET
DMARQ
-DMACK
-DASP
-CD1, -CD2
Function
Address group. Use by host to select the register or data port that will be
accessed.
Asserted by host to read register or data port.
Asserted by host to write register or data port.
Interrupt request to the host.
Hardware reset signal.
Asserted by device when it is ready for a DMA transfer.
DMA acknowledge signal asserted by host in response to DMARQ.
Disk Active/Slav Present signal in Master/Slave handshake protocol.
Chip detect.
The host controls the device via 8 registers (see Figure 11-3). Seven of these registers
comprise the command block: FR, SC, SN, CYL, CYH, DH and CMD. The command block
registers are written, in sequence, to execute a command. Afterwards, the error and status
register return to the host a failure indicator or otherwise signal device operation
completion. The need to poll these registers is removed if the host is instead alerted by an
interrupt request (on the INTRQ signal) to attend to the device.
Up to two devices, known as master and slave (or device 0 and device 1) may be located on
a single conventional bus. The active device (the target for the next command) is selected
by the DEV bit in the DH register, and generally only one device can be accessed at a time,
meaning that a read or write to one cannot interrupt a read or write to the other.
129
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